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Data Sheet, Rev. 0.5, Dec. 2003
HYS72D128300GBR-[5/6/7]-B HYS72D256320GBR-[5/6/7]-B HYS72D128500HR-[7F/7]-B HYS72D128321GBR-[5/6/7]-B
184-Pin Registered Double Data Rate SDRAM Module Reg DIMM DDR SDRAM Green Product Lead Containing Product
Memory Products
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Edition 2003-12 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany (c) Infineon Technologies AG 2003. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Data Sheet, Rev. 0.5, Dec. 2003
HYS72D128300GBR-[5/6/7]-B HYS72D256320GBR-[5/6/7]-B HYS72D128500HR-[7F/7]-B HYS72D128321GBR-[5/6/7]-B
184-Pin Registered Double Data Rate SDRAM Module Reg DIMM
Memory Products
Never
stop
thinking.
HYS72D128300GBR-[5/6/7]-B, HYS72D256320GBR-[5/6/7]-B, HYS72D128500HR-[7F/7]-B Revision History: Previous Version: Page Subjects (major changes since last revision) Rev. 0.5 2003-12
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Template: mp_a4_v2.0_2003-06-06.fm
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
1 1.1 1.2 2 3 3.1 4 5 6
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Application Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Data Sheet
5
Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
Overview
1
1.1
* * * * * * * * * * * *
Overview
Features
184-pin Registered 8-Byte Dual-In-Line DDR SDRAM Module for "1U" PC, Workstation and Server main memory applications One rank 128M x 72 organization and two rank 256M x 72 organization JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) with a single + 2.5 V ( 0.2 V) power supply and +2.6( 0.1 V) power supply for DDR400 Built with DDR SDRAMs in 66-Lead TSOPII and FBGA 60 package Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) Auto Refresh (CBR) and Self Refresh All inputs and outputs SSTL_2 compatible Re-drive for all input signals using register and PLL devices. Serial Presence Detect with E2PROM Low Profile Modules form factor: 133.35 mm x 28.58 mm (1.1") x 4.00 mm and 133.35 mm x 30.48 mm (1.2") x 4.00 mm Based on Jedec standard reference card layout RawCard "B", "C" and "D" Gold plated contacts Performance -5 DDR400B -6 DDR333B 166 166 133 -7 DDR266A -- 143 133 -7F DDR266 -- 143 133 Unit -- MHz MHz MHz Component Module
Table 1
Part Number Speed Code Speed Grade
PC3200-3033 PC2700-2533 PC2100-2033 PC2100-2022 --
max. Clock Frequency @ CL = 3
fCK3 200 @ CL = 2.5 fCK2.5 166 @ CL = 2 fCK2 133
1.2
Description
The HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B are low profile versions of the standard Registered DIMM modules with 1.1" inch (28.58) and 1.2" inch (30,40 mm) height for 1U Server Applications. The Low Profile DIMM versions are available as 128M x 72 (1 GB) and 256M x 72 (2 GB). The memory array is designed with Double Data Rate Synchronous DRAMs for ECC applications. All control and address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing. A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer.
Data Sheet
6
Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
Overview Table 2 Type Ordering Information1)2) Compliance Code2) Description SDRAM Technology
PC3200 (CL=3) HYS72D128300GBR-5-B HYS72D128321GBR-5-B HYS72D256320GBR-5-B PC2700 (CL=2.5) HYS72D128300GBR-6-B HYS72D128321GBR-6-B HYS72D256320GBR-6-B PC2100 (CL=2) HYS72D128300GBR-7-B HYS72D128321GBR-7-B HYS72D256320GBR-7-B PC2100R-20330-C0 PC2100R-20330-B0 PC2100R-20330-D0 one rank 1 GByte Reg. ECC DIMM 512 MBit (x4) two ranks1 GByte Reg. ECC DIMM 512 MBit (x8) two ranks 2 GByte Reg. ECC DIMM 512 MBit (x4) PC2700R-25330-C0 PC2700R-25330-B0 PC2700R-25330-D0 one rank 1 GByte Reg. ECC DIMM 512 MBit (x4) two ranks 1 GByte Reg. ECC DIMM 512 MBit (x8) two ranks 2 GByte Reg. ECC DIMM 512 MBit (x4) PC3200R-30331-C0 PC3200R-30331-B0 PC3200R-30331-D0 one rank 1 GByte Reg. ECC DIMM 512 MBit (x4) two ranks 1 GByte Reg. ECC DIMM 512 MBit (x8) two ranks 2 GByte Reg. ECC DIMM 512 MBit (x4)
HYS72D128500HR-7F-B HYS72D128500HR-7-B
PC2100R-20220-M PC2100R-20330-M
one rank 1GByte Reg. ECC DIMM 512 MBit (x4) one rank 1GByte Reg. ECC DIMM 512 MBit (x4)
1) All part numbers end with a place code (not shown), designating the silicon-die revision. Reference information available on request. Example: HYS72D128300GBR-[5/6/7]-B, indicating Rev.B die are used for SDRAM components. 2) The Compliance Code is printed on the module labels and describes the speed sort for example "PC2100R", the latencies (for example "20330" means CAS latency = 2.5, tRCD latency = 3 and tRP latency =3 ) and the Raw Card used for this module
Data Sheet
7
Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
Pin Configuration
2
Table 3 Symbol
Pin Configuration
Pin Definitions and Functions Type Function Address Inputs Bank Selects Data Input/Output Check Bits (x72 organization only) Command Inputs Clock Enable SDRAM low data strobes Differential Clock Input SDRAM low data mask/ high data strobes Chip Selects Power (+2.5 V) Ground I/O Driver power supply VDD Indentification flag EEPROM power supply I/O reference supply Serial bus clock Serial bus data line slave address select no connect don't use Reset pin (forces register inputs low)1)
A0 - A11,A12 BA0, BA1 DQ0 - DQ63 CB0 - CB7 RAS,CAS,WE CKE0, CKE1 DQS0 - DQS8 CK0, CK0 DM0 - DM8 DQS9 - DQS17 S0 - S1
VDD VSS VDDQ VDDID VDDSPD VREF
SCL SDA SA0 - SA2 NC DU RESET
1) for detailed description of the Power Up and Power Management on DDR Registered DIMMs see the Application Note at the end of this datasheet
Data Sheet
8
Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
Pin Configuration Table 4 PIN# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Data Sheet Pin Configuration1) Symbol PIN# 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 Symbol A0 CB2 PIN# 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 9 Symbol DQ4 DQ5 PIN# 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 Symbol A10 CB6
VREF
DQ0
VSS
DQ1 DQS0 DQ2
VSS
CB3 BA1 KEY DQ32
VDDQ
DQS9 DQ6 DQ7
VDDQ
CB7 KEY
VSS
DQ36 DQ37
VDD
DQ3 NC RESET
VSS
NC NC NC
VDDQ
DQ33 DQS4 DQ34
VDD
DM4/DQS13 DQ38 DQ39
VSS
DQ8 DQ9 DQS1
VDDQ
DQ12 DQ13 DQS10
VSS
BA0 DQ35 DQ40
VSS
DQ44 RAS DQ45
VDDQ
DU DU
VDD
DQ14 DQ15 CKE1
VDDQ
WE DQ41 CAS
VDDQ
S0 S1 DQS14
VSS
DQ10 DQ11 CKE0
VDDQ
NC DQ20 NC / A12
VSS
DQS5 DQ42 DQ43
VSS
DQ46 DQ47 NC
VDDQ
DQ16 DQ17 DQS2
VSS
DQ21 A11 DQS11
VDD
NC DQ48 DQ49
VDDQ
DQ52 DQ53 NC
VSS
A9 DQ18 A7
VDD
DQ22 A8 DQ23
VSS
DU DU
VDD
DQS15 DQ54 DQ55
VDDQ
DQ19 A5 DQ24
VDDQ
DQS6 DQ50 DQ51
VSS
A6 DQ28 DQ29
VDDQ
NC DQ60 DQ61
VSS
DQ25 DQS3 A4
VSS VDDID
DQ56 DQ57
VDDQ
DQS12 A3 DQ30
VSS
DQS16 DQ62 DQ63
VDD
DQ26 DQ27 A2
VDD
DQS7 DQ58
VSS
DQ31 CB4
VDDQ
Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
Pin Configuration Table 4 PIN# 42 43 44 45 46 47 Pin Configuration1) (cont'd) Symbol PIN# 88 89 90 91 92 93 Symbol DQ59 PIN# 135 136 137 138 139 140 Symbol CB5 PIN# 181 182 183 184 - - Symbol SA0 SA1 SA2
VSS
A1 CB0 CB1
VSS
NC SDA SCL
VDDQ
CK0 CK0
VDDSPD
- -
VDD
DQS8
VSS
DQS17
VSS
1) A12 is used for 256Mbit and 512Mbit based modules only.
Table 5
Address Format Memory Ranks 1 2 2 SDRAMs # of SDRAMs 18 # of row/bank/ column bits 13/2/12 13/2/11 13/2/12 Refresh 8K 8K 8K Period Interval 64 ms 64 ms 64 ms 7.8 s 7.8 s 7.8 s
Density Organization 1 GB 1 GB 2 GB 128M x 72 128M x 72 256M x 72
128M x 4 18 64M x 8 128M x 4 36
Data Sheet
10
Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
Pin Configuration
VSS RS0
DQS0
DQ0 DQ1 DQ2 DQ3 DQS I/O 0 I/O 1 I/O 2 I/O 3 S DM
DM0/DQS9
DQ4 DQ5 DQ6 DQ7 DQS I/O 0 I/O 1 I/O 2 I/O 3 S DM
D0
D9
DQS1
DQ8 DQ9 DQ10 DQ11 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 S DM
DM1/DQS10
DQS DQ12 DQ13 DQ14 DQ15 I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 S DM
D1
D10
DQS2
S DM DQ16 DQ17 DQ18 DQ19
DM2/DQS11
S DM DQ20 DQ21 DQ22 DQ23
D2
D11
DQS3
S DM DQ24 DQ25 DQ26 DQ27
DM3/DQS12
S DM
D3
DQ28 DQ29 DQ30 DQ31
D12
DQS4
DQ32 DQ33 DQ34 DQ35 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 S DM
DM4/DQS13
D4
DQ36 DQ37 DQ38 DQ39 DM
DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3
S
DM
VDDSPD
Serial PD D0-D17 D0-D17 D0-D17 D0-D17 Strap: see Note 4
VDDQ D13 VDD VREF
S DM
DQS5
S DQ40 DQ41 DQ42 DQ43
DM5/DQS14
DQ44 DQ45 DQ46 DQ47
VSS VDDID
D5
D14
DQS6
S DM DQ48 DQ49 DQ50 DQ51
DM6/DQS15
DQ52 DQ53 DQ54 DQ55
Serial PD
DQS S I/O 0 I/O 1 D15 I/O 2 I/O 3 S DM
SCL WP A0 A1 A2
SDA SA0 SA1 SA2
D6
DQS7
DQ56 DQ57 DQ58 DQ59 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 S DM
DM7/DQS16
D7
DQ60 DQ61 DQ62 DQ63 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DM
D16
DQS8
S
DM8/DQS17
CB4 CB5 CB6 CB7
S
DM
CB0 CB1 CB2 CB3
D8
D17
S0 BA0-BA1 A0-A136 RAS CAS CKE0 WE PCK PCK
R E G I S T E R
RS0 -> CS : SDRAMs D0-D17 RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D17 RA0-RA136 -> A0-A136: SDRAMs D0-D17 RRAS -> RAS: SDRAMs D0-D17 RCAS -> CAS: SDRAMs D0-D17 RCKE0A -> CKE: SDRAMs D0-D17 CK0, CK0 --------- PLL* RWE -> WE: SDRAMs D0-D17 * Wire per Clock Loading Table/Wiring Diagrams RESET
Notes: 1. DQ-to-I/O wiring may be changed within a byte. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ/DQS resistors should be 22 Ohms. 4. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD VDDQ. 5. Address and control resistors should be 22 Ohms. 6. A13 is not wired for raw card B.
Figure 1
Block Diagram: 1 Rank 128M x 72 DDR SDRAM DIMM HYS72D128[300/500]GBR-[5/6/7/7F]-B
Data Sheet
11
Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
Pin Configuration
RS1 RS0 DQS0 DM0/DQS9
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS
DQS4 DM4/DQS13
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS
D0
D9
D4
D13
DQS1 DM1/DQS10
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS
DQS5 DM5/DQS14
D1
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS
D10
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS DQS
D5
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS DQS
D14
DQS2 DM2/DQS11
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS
DQS
DQS6 DM6/DQS15
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS
D2
D11
D6
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS
DQS
D15
DQS3 DM3/DQS12
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS
DQS7 DM7DQS16
D3
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
D12
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS DQS
D7
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS DQS
D16
DQS8 DM8/DQS17
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS
D8
S0 S1 BA0-BA1 A0-A137 RAS CAS CKE0 CKE1 WE PCK PCK
R E G I S T E R
Strap: see Note 4 CK0, CK0 --------- PLL* RS0 -> CS : SDRAMs D0-D8 * Wire per Clock Loading Table/Wiring Diagrams RS1 -> CS : SDRAMs D9-D17 Notes: RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D17 1. DQ-to-I/O wiring may be changed within a byte. RA0-RA137 -> A0-A137: SDRAMs D0-D17 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. RRAS -> RAS: SDRAMs D0-D17 3. DQ/DQS resistors should be 22 Ohms. RCAS -> CAS: SDRAMs D0-D17 4. VDDID strap connections (for memory device VDD, VDDQ): RCKE0 -> CKE: SDRAMs D0-D8 STRAP OUT (OPEN): VDD = VDDQ RCKE1 -> CKE: SDRAMs D9-D17 STRAP IN (VSS): VDD VDDQ. RWE -> WE: SDRAMs D0-D17 5. RS0 and RS1 alternate between the back and front sides of the DIMM. 6. Address and control resistors should be 22 Ohms. RESET
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS
DQS VDDSPD
Serial PD SCL WP A0 A1 A2 SDA SA0 SA1 SA2
D17
VDDQ VDD VREF VSS VDDID
Serial PD D0-D17 D0-D17 D0-D17 D0-D17
7. A13 is not wired for raw card A.
Figure 2
Block Diagram - 2 Ranks 64M x 72 DDR SDRAM HYS72D128321GBR-[5/6/7]-B
Data Sheet
12
Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
Pin Configuration
VSS RS1 RS0 DQS0
DQ0 DQ1 DQ2 DQ3 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM
DM0/DQS9
DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQ4 DQ5 DQ6 DQ7 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM
D0
D18
D9
D27
DQS1
DQ8 DQ9 DQ10 DQ11 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM
DM1/DQS10
D1
DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM DQ12 DQ13 DQ14 DQ15
D19
DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3
CS
DM
D10
DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3
CS
DM
D28
DQS2
CS DM CS DM DQ16 DQ17 DQ18 DQ19
DM2/DQS11
CS DM CS DM
D2
D20
DQ20 DQ21 DQ22 DQ23
D11
D29
DQS3
CS DM DQ24 DQ25 DQ26 DQ27 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM
DM3/DQS12
CS DM CS DM
D3
D21
DQ28 DQ29 DQ30 DQ31
D12
D30
DQS4
DQ32 DQ33 DQ34 DQ35 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM
DM4/DQS13
D4
DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM DQ36 DQ37 DQ38 DQ39 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM DQS I/O 0 I/O 1 I/O 2 I/O 3 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM
D22
D13
D31
DQS5
CS DM CS DQ40 DQ41 DQ42 DQ43
DM5/DQS14
DQ44 DQ45 DQ46 DQ47
CS
CS
DM
D5
D23
D14
D32
DQS6
DQ48 DQ49 DQ50 DQ51 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM CS DM
DM6/DQS15
CS CS DM
D6
D24
DQ52 DQ53 DQ54 DQ55
D15
D33
DQS7
DQ56 DQ57 DQ58 DQ59 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM
DM7/DQS16
D7
DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM DQ60 DQ61 DQ62 DQ63
D25
DQS I/O 0 I/O 1 I/O 2 I/O 3
CS
DM
D16
DQS I/O 0 I/O 1 I/O 2 I/O 3
CS
DM
D34
DQS8
CB0 CB1 CB2 CB3 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM
DM8/DQS17
D8
DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM CB4 CB5 CB6 CB7
D26
DQS I/O 0 I/O 1 I/O 2 I/O 3
CS
DM
D17
DQS I/O 0 I/O 1 I/O 2 I/O 3
CS
DM
D35
CK0, CK0 --------- PLL* * Wire per Clock Loading Table/Wiring Diagrams SCL S0 S1 BA0-BA1 A0-A13 RAS CAS CKE0 CKE1 WE PCK PCK RSO -> CS : SDRAMs D0-D17 RS1 -> CS: SDRAMs D18-D35 RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D35 RA0-RA13 -> A0-A13: SDRAMs D0- D35 RRAS -> RAS: SDRAMs D0-D35 RCAS -> CAS: SDRAMs D0-D35 RCKE0 -> CKE: SDRAMs D0-D17 RCKE1 -> CKE: SDRAMs D18-D35 RWE -> WE: SDRAMs D0-D35 RESET
Serial PD
VDDSPD
WP A0
A1
A2
R E G I S T E R
SA0 SA1 SA2
VDDQ SDA VDD VREF VSS VDDID
Serial PD D0-D35 D0-D35 D0-D35 D0-D35 Strap: see Note 4
Notes:
1. DQ-to-I/O wiring may be changed within a byte. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ/DQS resistors should be 22 Ohms. 4. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD VDDQ. 5. Address and control resistors should be 22 Ohms. 6. Each Chip Select and CKE pair alternate between decks for thermal enhancement.
Figure 3
Block Diagram - 2 Ranks 128M x 72 DDR SDRAM HYS72D256320GBR-[5/6/7]-B
Data Sheet
13
Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
Electrical Characteristics
3
3.1
Table 6 Parameter
Electrical Characteristics
Operating Conditions
Absolute Maximum Ratings Symbol min. Values typ. - - - - - - 1 50 max. -0.5 -1 -1 -1 0 -55 - - Unit Note/ Test Condition V V V V C C W mA - - - - - - - -
Voltage on I/O pins relative to VSS Voltage on inputs relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Operating temperature (ambient) Storage temperature (plastic) Power dissipation (per SDRAM component) Short circuit output current
VIN, VOUT VIN VDD VDDQ TA TSTG PD IOUT
VDDQ +
0.5 +3.6 +3.6 +3.6 +70 +150 - -
Attention: Permanent damage to the device may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only, and functional operation should be restricted to recommended operation conditions. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit. Table 7 Parameter Device Supply Voltage Electrical Characteristics and DC Operating Conditions Symbol Min. 2.3 2.5 2.3 2.5 2.3 0 Values Typ. 2.5 2.6 2.5 2.6 2.5 Max. 2.7 2.7 2.7 2.7 3.6 0 V V V V V V Unit Note/Test Condition 1)
VDD Device Supply Voltage VDD Output Supply Voltage VDDQ Output Supply Voltage VDDQ EEPROM supply voltage VDDSPD Supply Voltage, I/O Supply VSS, Voltage VSSQ Input Reference Voltage VREF I/O Termination Voltage VTT
(System) Input High (Logic1) Voltage VIH(DC) Input Low (Logic0) Voltage VIL(DC) Input Voltage Level, CK and CK Inputs Input Differential Voltage, CK and CK Inputs VI-Matching Pull-up Current to Pull-down Current
fCK 166 MHz fCK > 166 MHz 2) fCK 166 MHz 3) fCK > 166 MHz 2)3)
-- --
4) 5)
0.49 x VDDQ 0.5 x VDDQ 0.51 x VDDQ V
VREF - 0.04 VREF + 0.15
-0.3 -0.3 0.36 0.71
VREF + 0.04 V VDDQ + 0.3 V VREF - 0.15 V VDDQ + 0.3 V VDDQ + 0.6
1.4 V --
8) 8) 8)
VIN(DC) VID(DC)
VIRatio
8)6)
7)
Data Sheet
14
Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
Electrical Characteristics Table 7 Parameter Input Leakage Current Electrical Characteristics and DC Operating Conditions (cont'd) Symbol Min. Values Typ. Max. 2 A Any input 0 V VIN VDD; All other pins not under test = 0 V 8)9) DQs are disabled; 0 V VOUT VDDQ -2 Unit Note/Test Condition 1)
II
Output Leakage Current Output High Current, Normal Strength Driver Output Low Current, Normal Strength Driver
1) 0 C TA 70 C
IOZ IOH IOL
-5 -- 16.2
5 -16.2 --
A mA mA
VOUT = 1.95 V VOUT = 0.35 V
2) DDR400 conditions apply for all clock frequencies above 166 MHz 3) Under all conditions, VDDQ must be less than or equal to VDD. 4) Peak to peak AC noise on VREF may not exceed 2% VREF (DC). VREF is also expected to track noise variations in VDDQ. 5) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 6) VID is the magnitude of the difference between the input level on CK and the input level on CK. 7) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. 8) Inputs are not recognized as valid until VREF stabilizes. 9) Values are shown per DDR SDRAM component
Data Sheet
15
Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
Electrical Characteristics
Table 8 Parameter
IDD Conditions
Symbol
Operating Current 0 one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. Operating Current 1 one bank; active/read/precharge; Burst Length = 4; see component data sheet. Precharge Power-Down Standby Current all banks idle; power-down mode; CKE VIL,MAX Precharge Floating Standby Current CS VIH,,MIN, all banks idle; CKE VIH,MIN; address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM. Precharge Quiet Standby Current CS VIHMIN, all banks idle; CKE VIH,MIN; VIN = VREF for DQ, DQS and DM; address and other control inputs stable at VIH,MIN or VIL,MAX. Active Power-Down Standby Current one bank active; power-down mode; CKE VILMAX; VIN = VREF for DQ, DQS and DM. Active Standby Current one bank active; CS VIH,MIN; CKE VIH,MIN; tRC = tRAS,MAX; DQ, DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle. Operating Current Read one bank active; Burst Length = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA Operating Current Write one bank active; Burst Length = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B Auto-Refresh Current tRC = tRFCMIN, burst refresh Self-Refresh Current CKE 0.2 V; external clock on Operating Current 7 four bank interleaving with Burst Length = 4; see component data sheet.
IDD0
IDD1 IDD2P IDD2F
IDD2Q
IDD3P IDD3N
IDD4R
IDD4W
IDD5 IDD6 IDD7
Data Sheet
16
Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
Electrical Characteristics
Table 9
IDD Specification for -7
HYS72D128500HR-7-B HYS72D128300GBR-7-B HYS72D128321GBR-7-B HYS72D256320GBR-7-B HYS72D128500HR-7F-B Unit Note 1)2)
Part Number & Organization
1 GB x72 1 Rank -7F typ. 2158 2354 430 736 646 538 934 2179 2273 4499 414 5493 max. 2452 2746 448 808 754 610 1042 2460 2554 5263 468 6376
1 GB x72 1 Rank -7 typ. 2028 2208 430 736 646 538 934 2118 2208 4278 414 5088 max. 2298 2568 448 808 754 610 1042 2388 2478 4998 468 5898
1 GB x72 2 Ranks -7 typ. 1587 1677 430 736 646 538 934 1632 1677 2712 414 3117 max. 1776 1911 448 808 754 610 1042 1821 1866 3126 468 3576
2 GB x72 2 Ranks -7 typ. 2586 2766 484 1096 916 700 1492 2676 2766 4836 451 5646 max. 2964 3234 520 1240 1132 844 1708 3054 3144 5664 560 6564 mA mA mA mA mA mA mA mA mA mA mA mA
3) 3)4) 5) 5) 5) 5) 5) 3)4) 3) 3) 5) 3)4)
Symbol
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
1) DRAM component currents only 2) Test condition for maximum values: VDD = 2.7 V, TA = 10 C 3) The module IDDx values are calculated from the component IDDx data sheet values as: m x IDDx[component] + n x IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules 4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) x IDDx[component]
Data Sheet
17
Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
Electrical Characteristics
Table 10
IDD Specification for -6
HYS72D128300GBR-6-B HYS72D128321GBR-6-B HYS72D256320GBR-6-B Unit Note 1)2)
Part Number & Organization
1GB x72 1 Rank -6 typ. 2350 2620 484 880 736 628 1096 2620 2710 4690 475 6310 max. 2710 2980 502 970 862 700 1222 2980 3070 5500 523.6 7300
1 GB x72 2 Ranks -6 typ. 1873 2008 484 880 736 628 1096 2008 2053 3043 475 3853 max. 2116 2251 502 970 862 700 1222 2251 2296 3511 523.6 4411
2 GB x72 2 Ranks -6 typ. 3016 3286 538 1330 1042 826 1762 3286 3376 5356 520 6976 max. 3502 3772 574 1510 1294 970 2014 3772 3862 6292 617.2 8092 mA mA mA mA mA mA mA mA mA mA mA mA
3) 3)4) 5) 5) 5) 5) 5) 3)4) 3) 3) 5) 3)4)
Symbol
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
1) DRAM component currents only 2) Test condition for maximum values: VDD = 2.7 V, TA = 10 C 3) The module IDDx values are calculated from the component IDDx data sheet values as: m x IDDx[component] + n x IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules 4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) x IDDx[component]
Data Sheet
18
Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
Electrical Characteristics
Table 11
IDD Specification for -5
HYS72D128300GBR-5-B HYS72D128321GBR-5-B HYS72D256320GBR-5-B Unit Note 1)2)
Part Number & Organization
1 GB x72 1 Rank -5 typ. 2680 2950 698 1184 986 860 1400 3040 3130 5290 696.2 7090 max. 3040 3400 734 1292 1112 932 1544 3490 3580 6190 737.6 8260
1 GB x72 2 Ranks -5 typ. 3436 3706 752 1724 1328 1076 2156 3796 3886 6046 748.4 7846 max. 3940 4300 824 1940 1580 1220 2444 4390 4480 7090 831.2 9160
2 GB x72 2 Ranks -5 typ. 3436 3706 752 1724 1328 1076 2156 3796 3886 6046 748.4 7846 max. 3940 4300 824 1940 1580 1220 2444 4390 4480 7090 831.2 9160 mA mA mA mA mA mA mA mA mA mA mA mA
3) 3)4) 5) 5) 5) 5) 5) 3)4) 3) 3) 5) 3)4)
Symbol
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
1) DRAM component currents only 2) Test condition for maximum values: VDD = 2.7 V, TA = 10 C 3) The module IDDx values are calculated from the component IDDx data sheet values as: m x IDDx[component] + n x IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules 4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) x IDDx[component]
Data Sheet
19
Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
Electrical Characteristics
Table 12 Parameter
AC Timing - Absolute Specifications -6/-5 Symbol Min. -5 DDR400B Max. +0.6 +0.5 0.55 0.55 12 12 12 -- -- -- -- +0.6 +0.6 1.25 +0.40 +0.40 +0.50 +0.50 -- -- -- -- -- 0.60 -- -- -- -- -- 1.1 0.60 Min. -0.7 -0.6 0.45 0.45 -- 6 7.5 0.45 0.45 2.2 1.75 -0.7 -0.7 0.75 -- -- -- -- 0.35 0.2 0.2 2 0 0.40 0.25 0.75 0.8 0.75 0.8 0.9 0.40 -6 DDR333 Max. +0.7 +0.6 0.55 0.55 -- 12 12 -- -- -- -- +0.7 +0.7 1.25 +0.40 +0.45 +0.50 +0.55 -- -- -- -- -- 0.60 -- -- -- -- -- 1.1 0.60 ns ns
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
Unit Note/ Test Condition 1)
DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width Clock Half Period Clock cycle time
tAC tDQSCK tCH tCL tHP tCK
-0.6 -0.5 0.45 0.45 5 6 7.5
tCK tCK
ns ns ns ns ns ns ns ns ns
min. (tCL, tCH)
min. (tCL, tCH) ns
CL = 3.0 2)3)4)5) CL = 2.5 2)3)4)5) CL = 2.0 2)3)4)5)
2)3)4)5) 2)3)4)5) 2)3)4)5)6)
DQ and DM input hold time DQ and DM input setup time Control and Addr. input pulse width (each input) DQ and DM input pulse width (each input)
tDH tDS tIPW
0.4 0.4 2.2 1.75 -0.6 -0.6 0.75 -- -- -- --
tDIPW Data-out high-impedance time from CK/CK tHZ Data-out low-impedance time from CK/CK tLZ st Write command to 1 DQS latching transition tDQSS DQS-DQ skew (DQS and associated DQ tDQSQ
signals) Data hold skew factor DQ/DQS output hold time
2)3)4)5)6) 2)3)4)5)7) 2)3)4)5)7) 2)3)4)5)
tCK
ns ns ns ns ns
TFBGA 2)3)4)5) TSOPII 2)3)4)5) TFBGA 2)3)4)5) TSOPII 2)3)4)5)
2)3)4)5) 2)3)4)5) 2)3)4)5)
tQHS
tQH DQS input low (high) pulse width (write cycle) tDQSL,H DQS falling edge to CK setup time (write tDSS
cycle) DQS falling edge hold time from CK (write cycle) Mode register set command cycle time Write preamble setup time Write postamble Write preamble Address and control input setup time
tHP -tQHS
0.35 0.2 0.2 2 0 0.40 0.25 0.6 0.7
tHP -tQHS
tCK tCK tCK tCK
ns
tDSH tMRD tWPRES tWPST tWPRE tIS
2)3)4)5)
2)3)4)5) 2)3)4)5)8) 2)3)4)5)9) 2)3)4)5)
tCK tCK
ns ns ns ns
fast slew rate
3)4)5)6)10)
slow slew rate
3)4)5)6)10)
Address and control input hold time
tIH
0.6 0.7
fast slew rate
3)4)5)6)10)
slow slew rate
3)4)5)6)10) 2)3)4)5) 2)3)4)5)
Read preamble Read postamble Data Sheet
tRPRE tRPST
0.9 0.40 20
tCK tCK
Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
Electrical Characteristics Table 12 Parameter AC Timing - Absolute Specifications -6/-5 (cont'd) Symbol Min. Active to Precharge command Active to Active/Auto-refresh command period Auto-refresh to Active/Auto-refresh command period Active to Read or Write delay Precharge command period Active to Autoprecharge delay Active bank A to Active bank B command Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Exit self-refresh to non-read command Exit self-refresh to read command Average Periodic Refresh Interval -5 DDR400B Max. 70E+3 -- -- -- -- -- -- -- Min. 42 60 72 18 18 18 12 15 -6 DDR333 Max. 70E+3 -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns
2)3)4)5) 2)3)4)5)
Unit Note/ Test Condition 1)
tRAS tRC tRFC tRCD tRP tRAP tRRD tWR tDAL tWTR tXSNR tXSRD tREFI
40 55 65 15 15 15 10 15
2)3)4)5)
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)11)
(tWR/tCK) + (tRP/tCK) 1 75 200 -- -- -- -- 7.8 1
(tWR/tCK) + (tRP/tCK) -- -- -- 7.8 75 200 --
tCK tCK
ns
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)12)
tCK
s
1) 0 C TA 70 C; VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V (DDR333); VDDQ = 2.6 V 0.1 V, VDD = +2.6 V 0.1 V (DDR400) 2) Input slew rate 1 V/ns for DDR400, DDR333 3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are 1.0 V/ns. 4) Inputs are not recognized as valid until VREF stabilizes. 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT. 6) These parameters guarantee device timing, but they are not necessarily tested on each device. 7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 10) Fast slew rate 1.0 V/ns , slow slew rate 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured between VOH(ac) and VOL(ac). 11) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Data Sheet
21
Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
Electrical Characteristics
Table 13 Parameter
AC Timing - Absolute Specifications -7/-7F Symbol Min. -7F DDR266 Max. Min. -7 DDR266A Max. ns ns
2)2)3)3)4)4)5)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
Unit Note/ Test Condition
1)1)
DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width Clock Half Period Clock cycle time
tAC tDQSCK tCH tCL tHP tCK
-0.75 +0.75 -0.75 +0.75 0.45 0.45 7.5 7.5 0.55 0.55 12 12 -- -- -- --
-0.75 +0.75 -0.75 +0.75 0.45 0.45 7.5 7.5 0.5 0.5 2.2 1.75 0.55 0.55 12 12 -- -- -- --
tCK tCK
ns ns ns ns ns ns ns ns ns
min. (tCL, tCH)
min. (tCL, tCH)
CL = 2.5
2)3)4)5)
CL = 2.0
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)6) 2)3)4)5)6) 2)3)4)5)7) 2)3)4)5)7) 2)3)4)5)
tDH DQ and DM input setup time tDS Control and Addr. input pulse width (each input) tIPW DQ and DM input pulse width (each input) tDIPW Data-out high-impedance time from CK/CK tHZ Data-out low-impedance time from CK/CK tLZ Write command to 1st DQS latching transition tDQSS DQS-DQ skew (DQS and associated DQ tDQSQ
DQ and DM input hold time signals)
0.5 0.5 2.2 1.75
-0.75 +0.75 -0.75 +0.75 0.75 -- -- 1.25 +0.5 +0.5 +0.75 +0.75
-0.75 +0.75 -0.75 +0.75 0.75 -- -- -- -- 1.25 +0.5 +0.5 +0.75 +0.75
tCK
ns ns ns ns ns
TFBGA
2)3)4)5)
TSOPII
2)3)4)5)
Data hold skew factor
tQHS
-- --
TFBGA
2)3)4)5)
TSOPII
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)8) 2)3)4)5)9) 2)3)4)5)
tQH DQS input low (high) pulse width (write cycle) tDQSL,H DQS falling edge to CK setup time (write cycle) tDSS DQS falling edge hold time from CK (write cycle) tDSH Mode register set command cycle time tMRD Write preamble setup time tWPRES Write postamble tWPST Write preamble tWPRE Address and control input setup time tIS
DQ/DQS output hold time
tHP - tQHS
0.35 0.2 0.2 2 0 0.40 0.25 0.9 -- -- -- -- -- 0.60 -- --
tHP - tQHS
0.35 0.2 0.2 2 0 0.40 0.25 0.9 -- -- -- -- -- 0.60 -- --
tCK tCK tCK tCK
ns
tCK tCK
ns
fast slew rate
3)4)5)6)10)
0.9
--
0.9
--
ns
slow slew rate
3)4)5)6)10)
Data Sheet
22
Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
Electrical Characteristics Table 13 Parameter AC Timing - Absolute Specifications -7/-7F Symbol Min. Address and control input hold time -7F DDR266 Max. -- Min. 0.9 -7 DDR266A Max. -- ns fast slew rate
3)4)5)6)10)
Unit Note/ Test Condition
1)1)
tIH
0.9
1.0
--
1.0
--
ns
slow slew rate
3)4)5)6)10) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
Read preamble Read postamble Active to Precharge command Active to Active/Auto-refresh command period Auto-refresh to Active/Auto-refresh command period Active to Read or Write delay
tRPRE tRPST tRAS tRC tRFC
0.9 0.40 45 65 75 20 20 20 15 15
1.1 0.60 -- -- -- -- -- -- --
0.9 0.40 65 75 20 20 20 15 15
1.1 0.60 -- -- -- -- -- -- --
tCK tCK
ns ns ns ns ns ns ns
120E+3 45
120E+3 ns
tRCD Precharge command period tRP Active to Autoprecharge delay tRAP Active bank A to Active bank B command tRRD Write recovery time tWR Auto precharge write recovery + precharge time tDAL
Internal write to read command delay Exit self-refresh to non-read command Exit self-refresh to read command Average Periodic Refresh Interval
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)11)
(tWR/tCK) + (tRP/tCK) 1 75 200 -- -- -- -- 7.8 1 75
(tWR/tCK) + (tRP/tCK) -- -- -- 7.8
tCK tCK
ns
tWTR tXSNR tXSRD tREFI
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)12)
200 --
tCK
s
1) 0 C TA 70 C; VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V (DDR333); VDDQ = 2.6 V 0.1 V, VDD = +2.6 V 0.1 V (DDR400) 2) Input slew rate 1 V/ns for DDR400, DDR333 3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are 1.0 V/ns. 4) Inputs are not recognized as valid until VREF stabilizes. 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT. 6) These parameters guarantee device timing, but they are not necessarily tested on each device. 7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 10) Fast slew rate 1.0 V/ns , slow slew rate 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured between VOH(ac) and VOL(ac).
Data Sheet
23
Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
Electrical Characteristics
11) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Data Sheet
24
Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
SPD Contents
4
Table 14
SPD Contents
SPD Codes for HYS72D[128/256][300/321/320]GBR-5-B HYS72D128300GBR-5-B HYS72D128321GBR-5-B HYS72D256320GBR-5-B 2 GB x72 2 Ranks -5 PC3200R-30331 Rev. 1.0 HEX 80 08 07 0D 0C 02 48 00 04 50 50 02 82 04 04 01 0E 04 1C 01 02 26 C1 60 50 75 Rev. 0.5, 2003-12
Part Number & Organization
1 GB x72 1 Rank -5 PC3200R-30331 Rev. 1.0 HEX 80 08 07 0D 0C 01 48 00 04 50 50 02 82 04 04 01 0E 04 1C 01 02 26 C1 60 50 75 25
1 GB x72 2 Ranks -5 PC3200R-30331 Rev. 1.0 HEX 80 08 07 0D 0B 02 48 00 04 50 50 02 82 08 08 01 0E 04 1C 01 02 26 C1 60 50 75
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Data Sheet Description Programmed SPD Bytes in E2PROM Total number of Bytes in E2PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] Error Correction Support (non- / ECC) Refresh Rate Primary SDRAM Width Error Checking SDRAM Width tCCD [cycles] Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes Component Attributes tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns]
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
SPD Contents Table 14 SPD Codes for HYS72D[128/256][300/321/320]GBR-5-B HYS72D128300GBR-5-B HYS72D128321GBR-5-B HYS72D256320GBR-5-B 2 GB x72 2 Ranks -5 PC3200R-30331 Rev. 1.0 HEX 50 3C 28 3C 28 01 60 60 40 40 00 37 41 28 28 50 00 01 00 10 E2 C1 00 xx 37 32 44 Rev. 0.5, 2003-12
Part Number & Organization
1 GB x72 1 Rank -5 PC3200R-30331 Rev. 1.0 HEX 50 3C 28 3C 28 01 60 60 40 40 00 37 41 28 28 50 00 01 00 10 E1 C1 00 xx 37 32 44 26
1 GB x72 2 Ranks -5 PC3200R-30331 Rev. 1.0 HEX 50 3C 28 3C 28 80 60 60 40 40 00 37 41 28 28 50 00 01 00 10 68 C1 00 xx 37 32 44
Label Code JEDEC SPD Revision Byte# 26 27 28 29 30 31 32 33 34 35 36 - 40 41 42 43 44 45 46 47 48 - 61 62 63 64 65 - 71 72 73 74 75 Data Sheet Description tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] Module Density per Rank tAS, tCS [ns] tAH, TCH [ns] tDS [ns] tDH [ns] not used tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] not used DIMM PCB Height not used SPD Revision Checksum of Byte 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
SPD Contents Table 14 SPD Codes for HYS72D[128/256][300/321/320]GBR-5-B HYS72D128300GBR-5-B HYS72D128321GBR-5-B HYS72D256320GBR-5-B 2 GB x72 2 Ranks -5 PC3200R-30331 Rev. 1.0 HEX 32 35 36 33 32 30 47 42 52 35 42 20 20 20 20 xx xx xx xx xx 00 Rev. 0.5, 2003-12
Part Number & Organization
1 GB x72 1 Rank -5 PC3200R-30331 Rev. 1.0 HEX 31 32 38 33 30 30 47 42 52 35 42 20 20 20 20 xx xx xx xx xx 00
1 GB x72 2 Ranks -5 PC3200R-30331 Rev. 1.0 HEX 31 32 38 33 32 31 47 42 52 35 42 20 20 20 20 xx xx xx xx xx 00
Label Code JEDEC SPD Revision Byte# 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 - 98 Description Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number (1 - 4)
99 - 127 not used
Data Sheet
27
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
SPD Contents
Table 15
SPD Codes for HYS72D[128/256][300/321/320]GBR-6-B HYS72D128300GBR-6-B HYS72D128321GBR-6-B HYS72D256320GBR-6-B 2 GB x72 2 Ranks -6 PC2700R-25330 Rev. 0.0 HEX 80 08 07 0D 0C 02 48 00 04 60 70 02 82 04 04 01 0E 04 0C 01 02 26 C1 75 70 00 Rev. 0.5, 2003-12
Part Number & Organization
1 GB x72 1 Rank -6 PC2700R-25330 Rev. 0.0 HEX 80 08 07 0D 0C 01 48 00 04 60 70 02 82 04 04 01 0E 04 0C 01 02 26 C1 75 70 00 28
1 GB x72 2 Ranks -6 PC2700R-25330 Rev. 0.0 HEX 80 08 07 0D 0B 02 48 00 04 60 70 02 82 08 08 01 0E 04 0C 01 02 26 C1 75 70 00
Label Code Jedec SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Data Sheet Description Programmed SPD Bytes in E2PROM Total number of Bytes in E2PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] Error Correction Support (non- / ECC) Refresh Rate Primary SDRAM Width Error Checking SDRAM Width tCCD [cycles] Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes Component Attributes tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns]
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
SPD Contents Table 15 SPD Codes for HYS72D[128/256][300/321/320]GBR-6-B HYS72D128300GBR-6-B HYS72D128321GBR-6-B HYS72D256320GBR-6-B 2 GB x72 2 Ranks -6 PC2700R-25330 Rev. 0.0 HEX 00 48 30 48 2A 01 75 75 45 45 00 3C 48 30 28 50 00 00 00 00 CB C1 00 xx 37 32 44 Rev. 0.5, 2003-12
Part Number & Organization
1 GB x72 1 Rank -6 PC2700R-25330 Rev. 0.0 HEX 00 48 30 48 2A 01 75 75 45 45 00 3C 48 30 28 50 00 00 00 00 CA C1 00 xx 37 32 44 29
1 GB x72 2 Ranks -6 PC2700R-25330 Rev. 0.0 HEX 00 48 30 48 2A 80 75 75 45 45 00 3C 48 30 28 50 00 00 00 00 51 C1 00 xx 37 32 44
Label Code Jedec SPD Revision Byte# 26 27 28 29 30 31 32 33 34 35 36 - 40 41 42 43 44 45 46 47 48 - 61 62 63 64 65 - 71 72 73 74 75 Data Sheet Description tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] Module Density per Rank tAS, tCS [ns] tAH, TCH [ns] tDS [ns] tDH [ns] not used tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] not used DIMM PCB Height not used SPD Revision Checksum of Byte 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2 - 8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
SPD Contents Table 15 SPD Codes for HYS72D[128/256][300/321/320]GBR-6-B HYS72D128300GBR-6-B HYS72D128321GBR-6-B HYS72D256320GBR-6-B 2 GB x72 2 Ranks -6 PC2700R-25330 Rev. 0.0 HEX 32 35 36 33 32 30 47 42 52 36 42 20 20 20 20 xx xx xx xx xx 00 Rev. 0.5, 2003-12
Part Number & Organization
1 GB x72 1 Rank -6 PC2700R-25330 Rev. 0.0 HEX 31 32 38 33 30 30 47 42 52 36 42 20 20 20 20 xx xx xx xx xx 00
1 GB x72 2 Ranks -6 PC2700R-25330 Rev. 0.0 HEX 31 32 38 33 32 31 47 42 52 36 42 20 20 20 20 xx xx xx xx xx 00
Label Code Jedec SPD Revision Byte# 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 - 98 Description Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number (1 - 4)
99 - 127 not used
Data Sheet
30
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
SPD Contents
Table 16
SPD Codes for HYS72D[128/256][300/321/320]GBR-7-B HYS72D128300GBR-7-B HYS72D128321GBR-7-B HYS72D256320GBR-7-B 2 GB x72 2 Ranks reg PC2100R-20330 Rev. 0.0 HEX 80 08 07 0D 0C 02 48 00 04 70 75 02 82 04 04 01 0E 04 0C 01 02 26 C1 75 75 00 Rev. 0.5, 2003-12
Part Number & Organization
1 GB x72 1 Rank reg PC2100R-20330 Rev. 0.0 HEX 80 08 07 0D 0C 01 48 00 04 70 75 02 82 04 04 01 0E 04 0C 01 02 26 C1 75 75 00 31
1 GB x72 2 Ranks reg PC2100R-20330 Rev. 0.0 HEX 80 08 07 0D 0B 02 48 00 04 70 75 02 82 08 08 01 0E 04 0C 01 02 26 C1 75 75 00
Label Code Jedec SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Data Sheet Description Programmed SPD Bytes in E2PROM Total number of Bytes in E2PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] Error Correction Support (non- / ECC) Refresh Rate Primary SDRAM Width Error Checking SDRAM Width tCCD [cycles] Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes Component Attributes tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns]
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
SPD Contents Table 16 SPD Codes for HYS72D[128/256][300/321/320]GBR-7-B HYS72D128300GBR-7-B HYS72D128321GBR-7-B HYS72D256320GBR-7-B 2 GB x72 2 Ranks reg PC2100R-20330 Rev. 0.0 HEX 00 50 3C 50 2D 01 90 90 50 50 00 41 4B 30 32 75 00 00 00 00 87 C1 00 xx 37 32 44 Rev. 0.5, 2003-12
Part Number & Organization
1 GB x72 1 Rank reg PC2100R-20330 Rev. 0.0 HEX 00 50 3C 50 2D 01 90 90 50 50 00 41 4B 30 32 75 00 00 00 00 86 C1 00 xx 37 32 44 32
1 GB x72 2 Ranks reg PC2100R-20330 Rev. 0.0 HEX 00 50 3C 50 2D 80 90 90 50 50 00 41 4B 30 32 75 00 00 00 00 0D C1 00 xx 37 32 44
Label Code Jedec SPD Revision Byte# 26 27 28 29 30 31 32 33 34 35 36 - 40 41 42 43 44 45 46 47 48 - 61 62 63 64 65 - 71 72 73 74 75 Data Sheet Description tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] Module Density per Rank tAS, tCS [ns] tAH, TCH [ns] tDS [ns] tDH [ns] not used tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] not used DIMM PCB Height not used SPD Revision Checksum of Byte 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2 - 8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
SPD Contents Table 16 SPD Codes for HYS72D[128/256][300/321/320]GBR-7-B HYS72D128300GBR-7-B HYS72D128321GBR-7-B HYS72D256320GBR-7-B 2 GB x72 2 Ranks reg PC2100R-20330 Rev. 0.0 HEX 32 35 36 33 32 30 47 42 52 37 42 20 20 20 20 xx xx xx xx xx 00 Rev. 0.5, 2003-12
Part Number & Organization
1 GB x72 1 Rank reg PC2100R-20330 Rev. 0.0 HEX 31 32 38 33 30 30 47 42 52 37 42 20 20 20 20 xx xx xx xx xx 00
1 GB x72 2 Ranks reg PC2100R-20330 Rev. 0.0 HEX 31 32 38 33 32 31 47 42 52 37 42 20 20 20 20 xx xx xx xx xx 00
Label Code Jedec SPD Revision Byte# 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 - 98 Description Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number (1 - 4)
99 - 127 not used
Data Sheet
33
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
SPD Contents
Table 17
SPD Codes for HYS72D128500HR-[7F/7]-B HYS72D128500HR-7F-B HYS72D128500HR-7-B 1 GB x72 1 Rank reg PC2100R-20330 Rev. 0.0 HEX 80 08 07 0D 0C 01 48 00 04 70 75 02 82 04 04 01 0E 04 0C 01 02 26 C1 75 75 00 Rev. 0.5, 2003-12
Part Number & Organization
1 GB x72 1 Rank reg PC2100R-20220 Rev. 0.0 HEX 80 08 07 0D 0C 01 48 00 04 70 75 02 82 04 04 01 0E 04 0C 01 02 26 C1 75 75 00 34
Label Code Jedec SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Data Sheet Description Programmed SPD Bytes in E2PROM Total number of Bytes in E2PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] Error Correction Support (non- / ECC) Refresh Rate Primary SDRAM Width Error Checking SDRAM Width tCCD [cycles] Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes Component Attributes tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns]
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
SPD Contents Table 17 SPD Codes for HYS72D128500HR-[7F/7]-B HYS72D128500HR-7F-B HYS72D128500HR-7-B 1 GB x72 1 Rank reg PC2100R-20330 Rev. 0.0 HEX 00 50 3C 50 2D 01 90 90 50 50 00 41 4B 30 32 75 00 00 00 00 86 C1 00 xx 37 32 44 Rev. 0.5, 2003-12
Part Number & Organization
1 GB x72 1 Rank reg PC2100R-20220 Rev. 0.0 HEX 00 3C 3C 3C 2D 01 90 90 50 50 00 3C 4B 30 32 75 00 00 00 00 59 C1 00 xx 37 32 44 35
Label Code Jedec SPD Revision Byte# 26 27 28 29 30 31 32 33 34 35 36 - 40 41 42 43 44 45 46 47 48 - 61 62 63 64 65 - 71 72 73 74 75 Data Sheet Description tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] Module Density per Rank tAS, tCS [ns] tAH, TCH [ns] tDS [ns] tDH [ns] not used tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] not used DIMM PCB Height not used SPD Revision Checksum of Byte 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2 - 8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
SPD Contents Table 17 SPD Codes for HYS72D128500HR-[7F/7]-B HYS72D128500HR-7F-B HYS72D128500HR-7-B 1 GB x72 1 Rank reg PC2100R-20330 Rev. 0.0 HEX 31 32 38 35 30 30 48 52 37 42 20 20 20 20 20 xx xx xx xx xx 00 Rev. 0.5, 2003-12
Part Number & Organization
1 GB x72 1 Rank reg PC2100R-20220 Rev. 0.0 HEX 31 32 38 35 30 30 48 52 37 46 42 20 20 20 20 xx xx xx xx xx 00
Label Code Jedec SPD Revision Byte# 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 - 98 99 - 127 Description Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number (1 - 4) not used
Data Sheet
36
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
Package Outlines
5
0.1 A B C
Package Outlines
133.35 128.95 4 MAX. A
4 0.1 28.58 0.13
0.15 A B C
1 2.5 0.1
o0.1 A B C
6.62 2.175 6.35
92
BC 0.4 1.27 0.1
64.77 95 x 1.27 = 120.65
49.53
3.8 0.13
1.8 0.1 93
0.1 A B C 184
10 17.8
L-DIM-184-22-2
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
Burr max. 0.4 allowed
Figure 4 Package Outline - Raw Card C DDR Registered DIMM HYS72D128300GBR-[5/6/7]-B
Data Sheet
37
Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
Package Outlines
0.1 A B C
133.35 128.95
0.15 A B C 4 MAX.
A
4 0.1
1 2.5 0.1
o0.1 A B C
6.62 2.175 6.35
92
28.58 0.13
BC 0.4 1.27 0.1 49.53 95 x 1.27 = 120.65 64.77 1.8 0.1 93 0.1 A B C 184
3.8 0.13
10
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
Burr max. 0.4 allowed
L-DIM-184-23-2
Figure 5
Package Outline - Raw Card B DDR Registered DIMM HYS72D128321HR-[5/6/7]-B
Data Sheet
38
Rev. 0.5, 2003-12
17.8
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
Package Outlines
0.1 A B C
133.35 128.95
0.15 A B C 4 MAX. A
4 0.1
1 2.5 0.1
92 o0.1 A B C 6.62 2.175 6.35 64.77 49.53
30.48 0.13
BC 0.4 1.27 0.1
3.8 0.13
1.8 0.1 93
0.1 A B C
184
10 17.8
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
Burr max. 0.4 allowed
Figure 6
L-DIM-184-25
Package Outline - Raw Card D DDR Registered DIMM HYS72D256320GBR-[5/6/7]-B
Data Sheet
39
Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
Package Outlines
0.1 A B C
133.35 128.95
0.15 A B C 4 MAX.
A
1)
4 0.1
1 2.5 0.1
o0.1 A B C
6.62 2.175 6.35
92
30.48 0.13
BC 0.4 1.27 0.1 49.53 95 x 1.27 = 120.65 64.77 1.8 0.1 93 0.1 A B C 184
3.8 0.13
10
3 MIN.
Detail of contacts
1)
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
1) On ECC modules only Burr max. 0.4 allowed
Figure 7
L-DIM-184-12-3
Package Outline - Raw Card M DDR Registered DIMM HYS72D128500HR-[7/7F]-B
Data Sheet
40
Rev. 0.5, 2003-12
17.8
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
Application Note
6
Application Note
Power Up and Power Management on DDR Registered DIMMs (according to JEDEC ballot JC-42.5 Item 1173) 184-pin Double Data Rate (DDR) Registered DIMMs include two new features to facilitate controlled power-up and to minimize power consumption during low power mode. One feature is externally controlled via a systemgenerated RESET signal; the second is based on module detection of the input clocks. These enhancements permit the modules to power up with SDRAM outputs in a High-Z state (eliminating risk of high current dissipations and/or dotted I/Os), and result in the powering-down of module support devices (registers and Phase-Locked Loop) when the memory is in Self-Refresh mode. The new RESET pin controls power dissipation on the module's registers and ensures that CKE and other SDRAM inputs are maintained at a valid `low' level during power-up and self refresh. When RESET is at a low level, all the register outputs are forced to a low level, and all differential register input receivers are powered down, resulting in very low register power consumption. The RESET pin, located on DIMM tab #10, is driven from the system as an asynchronous signal according to the attached details. Using this function also permits the system and DIMM clocks to be stopped during memory Self Refresh operation, while ensuring that the SDRAMs stay in Self Refresh mode. Table 18 RESET H H H H L The function for RESET is as follows:1) Register Outputs CK Rising Rising L or H High Z X or Hi-Z CK Falling Falling L or H High Z X or Hi-Z Data in (D) H L X X X or Hi-Z Data out (Q) H L Qo Illegal input conditions L
Register Inputs
1) X : Don't care, Hi-Z : High Impedance, Qo: Data latched at the previous of CK risning and CK falling
As described in the table above, a low on the RESET input ensures that the Clock Enable (CKE) signal(s) are maintained low at the SDRAM pins (CKE being one of the 'Q' signals at the register output). Holding CKE low maintains a high impedance state on the SDRAM DQ, DQS and DM outputs -- where they will remain until activated by a valid `read' cycle. CKE low also maintains SDRAMs in Self Refresh mode when applicable. The DDR PLL devices automatically detect clock activity above 20MHz. When an input clock frequency of 20MHz or greater is detected, the PLL begins operation and initiates clock frequency lock (the minimum operating frequency at which all specifications will be met is 95MHz). If the clock input frequency drops below 20MHz (actual detect frequency will vary by vendor), the PLL VCO (Voltage Controlled Oscillator) is stopped, outputs are made High-Z, and the differential inputs are powered down -- resulting in a total PLL current consumption of less than 1mA. Use of this low power PLL function makes the use of the PLL RESET (or G pin) unnecessary, and it is tied inactive on the DIMM. This application note describes the required and optional system sequences associated with the DDR Registered DIMM 'RESET' function. It is important to note that all references to CKE refer to both CKE0 and CKE1 for a 2bank DIMM. Because RESET applies to all DIMM register devices, it is therefore not possible to uniquely control CKE to one physical DIMM bank through the use of the RESET pin.
Data Sheet
41
Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
Application Note Power-Up Sequence with RESET -- Required 1. The system sets RESET at a valid low level. This is the preferred default state during power-up. This input condition forces all register outputs to a low state independent of the condition on the register inputs (data and clock), ensuring that CKE is at a stable low-level at the DDR SDRAMs. 2. The power supplies should be initialized according to the JEDEC-approved initialization sequence for DDR SDRAMs. 3. Stabilization of Clocks to the SDRAM The system must drive clocks to the application frequency (PLL operation is not assured until the input clock reaches 20MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices, and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM PLL, the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds. When a stable clock is present at the SDRAM input (driven from the PLL), the DDR SDRAM requires 200 sec prior to SDRAM operation. 4. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM connector). CKE must be maintained low and all other inputs should be driven to a known state. In general these commands can be determined by the system designer. One option is to apply an SDRAM `NOP' command (with CKE low), as this is the first command defined by the JEDEC initialization sequence (ideally this would be a `NOP Deselect' command). A second option is to apply low levels on all of the register inputs to be consistent with the state of the register outputs. 5. The system switches RESET to a logic `high' level. The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous, setting the RESET timing in relation to a specific clock edge is not required (during this period, register inputs must remain stable). 6. The system must maintain stable register inputs until normal register operation is attained. The registers have an activation time that allows their clock receivers, data input receivers, and output drivers sufficient time to be turned on and become stable. During this time the system must maintain the valid logic levels described in step 5. It is also a functional requirement that the registers maintain a low state at the CKE outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time (t (ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to accept an input signal, is specified in the register and DIMM do-umentation. 7. The system can begin the JEDEC-defined DDR SDRAM power-up sequence (according to the JEDECpproved initialization sequence).
Self Refresh Entry (RESET low, clocks powered off) -- Optional Self Refresh can be used to retain data in DDR SDRAM DIMMs even if the rest of the system is powered down and the clocks are off. This mode allows the DDR SDRAMs on the DIMM to retain data without external clocking. Self Refresh mode is an ideal time to utilize the RESET pin, as this can reduce register power consumption (RESET low deactivates register CK and CK, data input receivers, and data output drivers). 1. The system applies Self Refresh entry command. (CKELow, CSLow, RAS Low, CAS Low, WE High) Note: Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input conditions to the SDRAM are Don't Cares-- with the exception of CKE. 2. The system sets RESET at a valid low level. This input condition forces all register outputs to a low state, independent of the condition on the registerm inputs (data and clock), and ensures that CKE, and all other control and address signals, are a stable low-level at the DDR SDRAMs. Since the RESET signal is asynchronous, setting the RESET timing in relation to a specific clock edge is not required. 3. The system turns off clock inputs to the DIMM. (Optional) a. In order to reduce DIMM PLL current, the clock inputs to the DIMM are turned off, resulting in High-Z clock inputs to both the SDRAMs and the registers. This must be done after the RESET deactivate time of the register (t (INACT) ). The deactivate time defines the time in which the clocks and the control and address Data Sheet 42 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
Application Note signals must maintain valid levels after RESET low has been applied and is specified in the register and DIMM documentation. b. The system may release DIMM address and control inputs to High-Z. This can be done after the RESET deactivate time of the register. The deactivate time defines the time in which the clocks and the control and the address signals must maintain valid levels after RESET low has been applied. It is highly recommended that CKE continue to remain low during this operation. 4. The DIMM is in lowest power Self Refresh mode.
Self Refresh Exit (RESET low, clocks powered off) -- Optional 1. Stabilization of Clocks to the SDRAM. The system must drive clocks to the application frequency (PLL operation is not assured until the input clock reaches ~20MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices, and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM PLL, the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds. 2. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM connector). CKE must be maintained low and all other inputs should be driven to a known state. In general these commands can be determined by the system designer. One option is to apply an SDRAM `NOP' command (with CKE low), as this is the first command defined by the JEDEC Self Refresh Exit sequence (ideally this would be a `NOP Deselect' command). A second option is to apply low levels on all of the register inputs, to be consistent with the state of the register outputs. 3. The system switches RESET to a logic `high' level. The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous, RESET timing relationship to a specific clock edge is not required (during this period, register inputs must remain stable). 4. The system must maintain stable register inputs until normal register operation is attained. The registers have an activation time that allows the clock receivers, input receivers, and output drivers sufficient time to be turned on and become stable. During this time the system must maintain the valid logic levels described in Step 2. It is also a functional requirement that the registers maintain a low state at the CKE outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time (t (ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to accept an input signal, is specified in the register and DIMM do-umentation. 5. System can begin the JEDEC-defined DDR SDRAM Self Refresh Exit Procedure.
Self Refresh Entry (RESET low, clocks running) -- Optional Although keeping the clocks running increases power consumption from the on-DIMM PLL during self refresh, this is an alternate operating mode for these DIMMs. 1. System enters Self Refresh entry command. (CKE Low, CS Low, RAS Low, CAS Low, WE High) Note: Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input conditions to the SDRAM are Don't Cares -- with the exception of CKE. 2. The system sets RESET at a valid low level. This input condition forces all register outputs to a low state, independent of the condition on the data and clock register inputs, and ensures that CKE is a stable low-level at the DDR SDRAMs. 3. The system may release DIMM address and control inputs to High-Z. This can be done after the RESET deactivate time of the register (t (INACT) ). The deactivate time describes the time in which the clocks and the control and the address signals must maintain valid levels after RESET low has been applied. It is highly recommended that CKE continue to remain low during the operation. 4. The DIMM is in a low power, Self Refresh mode.
Data Sheet
43
Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B Registered Double Data Rate SDRAM Module
Application Note Self Refresh Exit (RESET low, clocks running) -- Optional 1. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM connector). CKE must be maintained low and all other inputs should be driven to a known state. In general these commands can be determined by the system designer. One option is to apply an SDRAM `NOP' command (with CKE low), as this is the first command defined by the Self Refresh Exit sequence (ideally this would be a `NOP Deselect' command). A second option is to apply low levels on all of the register inputs to be consistent with the state of the register outputs. 2. The system switches RESET to a logic 'high' level. The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous, it does not need to be tied to a particular clock edge (during this period, register inputs must continue to remain stable). 3. The system must maintain stable register inputs until normal register operation is attained. The registers have an activation time that allows the clock receivers, input receivers, and output drivers sufficient time to be turned on and become stable. During this time the system must maintain the valid logic levels described in Step 1. It is also a functional requirement that the registers maintain a low state at the CKE outputs in order to guarantee that the DDR SDRAMs continue to receive a low level on CKE. This activation time, from asynchronous switching of RESET from low to high, until the registers are stable and ready to accept an input signal, is t (ACT ) as specified in the register and DIMM documentation. 4. The system can begin JEDEC defined DDR SDRAM Self Refresh Exit Procedure.
Self Refresh Entry/Exit (RESET high, clocks running) -- Optional As this sequence does not involve the use of the RESET function, the JEDEC standard SDRAM specification explains in detail the method for entering and exiting Self Refresh for this case.
Self Refresh Entry (RESET high, clocks powered off) -- Not Permissible In order to maintain a valid low level on the register output, it is required that either the clocks be running and the system drive a low level on CKE, or the clocks are powered off and RESET is asserted low according to the sequence defined in this application note. In the case where RESET remains high and the clocks are powered off, the PLL drives a High-Z clock input into the register clock input. Without the low level on RESET an unknown DIMM state will result.
Data Sheet
44
Rev. 0.5, 2003-12
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Published by Infineon Technologies AG

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